Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. Switching activities of components in a target device put stress on a PDN supporting the target device. Target devices such as FPGAs do not consume power evenly. The changing states of logic and memory elements require the target device's PDN to supply more power than if the logic and memory elements were operating in a constant state. When a large number of logic and memory elements change state simultaneously, a large demand is placed on the PDN. Excessive voltage swings by the target device can lead to faulty operation of the target device.
To avoid unacceptable voltage deviations, a PDN should be properly decoupled over switching frequencies of the target device. On-board capacitors typically operate to decouple the PDN over a range of switching frequencies that cannot be decoupled by on-die or on-package capacitors of the target device. These decoupling capacitors store electric charge. When extra current is required from a PDN, the decoupling capacitors may meet some of the demand by discharging.
Current decoupling capacitor selection techniques require a designer to manually select the appropriate decoupling capacitors to add to a PDN. The iterative approach needed often requires a significant amount of time from the designer.